The present invention relates to power consumption of integrated circuit designs such as circuits used in medical devices, particularly implantable devices. More particularly, the present invention relates to utilizing adiabatic logic designs to minimize power dissipation in an implantable medical device.
Various devices require operation with low power consumption. For example, hand-held communication devices require such low power consumption and, in particular, implantable medical devices require low power capabilities. Implantable medical devices, for example, microprocessor-based implantable cardiac devices, such as implantable pacemakers and defibrillators, are required to operate with a lower power consumption to increase battery life and device longevity.
Generally, such low power devices are designed using complementary metal oxide semiconductor (CMOS) technology. CMOS technology is generally used because such technology has the characteristic of substantially zero xe2x80x9cstaticxe2x80x9d power consumption.
The power consumption of CMOS circuits consists generally of two power consumption factors, namely xe2x80x9cdynamicxe2x80x9d power consumption and xe2x80x9cstaticxe2x80x9d power consumption. Static power consumption is due to current leakage as the quiescent current of such circuits is zero. Dynamic power consumption is the dominant factor of power consumption for CMOS technology. Dynamic power consumption is basically due to the current required to charge internal and load capacitances during switching, i.e., the charging and discharging of such capacitances. The dynamic power (P) is equal to: CVDD2F, where C is the nodal capacitance, F is the clock or switching frequency, and VDD is the supply voltage for the CMOS circuit. As can be seen from the formula for calculating dynamic power (P), such dynamic power consumption of CMOS circuits is proportional to the square of the supply voltage (VDD). In addition, the dynamic power (P) is proportional to the nodal capacitance (C) and the switching or clock frequency (F).
In accordance with the formula for dynamic power consumption, it is effective conventionally in CMOS integrated circuit designs to scale down the supply voltage for an entire device (e.g., hybrid) or integrated circuit (IC), i.e., operate the circuit at low supply voltages, to reduce power consumption for such designs. For example, in the Medtronic Spectrax(copyright), circa 1979, IC circuitry is powered by one LiI cell versus two cells. This reduced the supply voltage to 2.8 volts from 5.6 volts, thus reducing overhead current. Voltages required to be greater than 2.8 volts are generated by a voltage doubler, or alternatively by a charge pump (e.g., output pacing pulses). Further, for example, in the Medtronic Symbios(copyright), circa 1983, the logic circuitry is powered by a voltage regulator controlling the IC supply voltage to a xe2x80x9csum of thresholdsxe2x80x9d supply. This regulator provides a supply to the IC (i.e., VDD) of several hundred millivolts above the sum of the n-channel and p-channel thresholds of the CMOS transistors making up the IC. This regulator is self-calibrating regarding manufacturing variations of the transistor thresholds.
Other devices reduce power consumption in other varied manners. For example, various device designs shutdown analog blocks and/or shut-off clocks to logic blocks not used at particular times, thereby reducing power. Further, for example, microprocessor-based devices historically use a xe2x80x9cburst clockxe2x80x9d design to operate a microprocessor at a very high clock rate (e.g., generally 500-1000 Kilohertz (kHz)), for relatively short periods of time to gain the benefit of a xe2x80x9cduty cyclexe2x80x9d to reduce average current drain. A much lower frequency clock (e.g., generally 32 kHz) is used for other circuitry and/or the processor when not in the high clock rate mode, i.e., burst clock mode. Many known processor-based implanted devices utilize the burst clock technique. For example, implanted devices available from Medtronic, Vitatron, Biotronic, ELA, Intermedics, Pacesetters, InControl, Cordis, CPI, etc., utilize burst clock techniques. A few illustrative examples which describe the use of a burst clock are provided in U.S. Pat. No. 4,561,442 to Vollmann et al., entitled xe2x80x9cImplantable Cardiac Pacer With Discontinuous Microprocessor Programmable Anti Tachycardia Mechanisms and Patient Data Telemetry,xe2x80x9d issued Dec. 31, 1985; U.S. Pat. No. 5,022,395 to Russie, entitled xe2x80x9cImplantable Cardiac Device With Dual Clock Control of Microprocessor,xe2x80x9d issued Jun. 11, 1991; U.S. Pat. No. 5,388,578 to Yomtov et al., entitled xe2x80x9cImproved Electrode System For Use With An Implantable Cardiac Patient Monitor,xe2x80x9d issued Feb. 14, 1995; and U.S. Pat. No. 5,154,170 to Bennett et al., entitled xe2x80x9cOptimization for Rate Responsive Cardiac Pacemaker,xe2x80x9d issued Oct. 13, 1992.
FIG. 1 represents a graphical illustration of energy/delay versus supply voltage for CMOS circuits such as a CMOS inverter 10 shown in FIG. 2 for illustrative purposes. The inverter 10 is provided with a supply voltage, VDD, which is connected to the source of a PMOS field effect transistor (FET) 12. PMOS FET 12 has its drain connected to the drain of an NMOS FET 14 whose source is connected to ground. In this configuration, an input Vi applied to both the gates of FETs 12, 14 is inverted to provide output Vo. Simply stated, with each clock cycle or logic level change, the input Vi is inverted and produces output Vo.
As shown in FIG. 1, the circuit logic delay increases drastically as the supply voltage is reduced to near one volt, as represented by delay line 16 and energy/delay line 18. As such, reducing of the supply voltage (VDD) continuously to lower levels is impractical because of the need for higher supply voltages when higher frequency operation is required. For example, generally CMOS logic circuits must periodically provide functionality at a higher frequency, e.g., burst clock frequency. However, as the supply voltage (VDD) is decreased, such energy consumption is reduced by the square of the supply voltage (VDD) as is shown by energy consumption line 20. Therefore, speed requires a higher supply voltage (VDD) which is in direct conflict with low power consumption.
Other problems are also evident when lower supply voltages (VDD) are used for CMOS circuit designs. When a lower supply voltage is selected, static leakage current losses may arise, particularly at lower frequencies, due to increased static leakage current losses.
Various techniques for reducing power consumption in devices are known in the art, some examples of which may be found in the references listed in Table 1 below.
All references listed in Table 1 herein above are hereby incorporated by reference in their respective entireties. As those of ordinary skill in the art will appreciate readily upon reading the Summary of the Invention, Detailed Description of the Embodiments, and claims set forth below, many of the devices and methods disclosed in the references of Table 1 and others incorporated by reference herein may be modified advantageously by using the teachings of the present invention.
Various embodiments of the present invention provide solutions to one or more problems existing in the prior art with respect to circuitry designs having power dissipation, particularly with respect to implantable medical devices. These problems include: (a) transistor circuits, including CMOS circuits, having a large power consumption which reduces battery life; (b) the inability to minimize power dissipation associated with interconnections of various elements or circuits; utilize low voltage supply levels effectively; (c) the inability to provide adequate processing capabilities such as high processing capabilities including telemetry uplink/downlink, morphology detection, initialization of devices, while still providing low processing capabilities such as sensing intrinsic beats, pacing, and low speed telemetry, with the desired power consumption; and (d) the inability to provide circuit designs that operate at lower frequencies and thus lower power consumption as opposed to the use of higher speed clocks such as burst clocks.
In comparison to known techniques for reducing power consumption in circuit designs, various embodiments of the present invention may provide one or more of the following advantages: (a) reduced power consumption through the use of adiabatic logic; (b) reduced power consumption due to a decreased lock frequency for circuit designs; (c) increased longevity of circuits, particularly implantable device circuitry; (d) reduced product size and minimization of static leakage current losses, i.e., static power consumption; and (e) multi-processor designs, DSP designs, and high performance processing designs with additional features/function opportunities due to the ability to reduce power dissipation associated with chip-to-chip and intrachip data and/or address bus signals.
Some embodiments of the invention include one or more of the following features: (a) an adiabatic logic design producing a ramp logic signal which minimizes power consumption; (b) circuitry designs which utilize an internal capacitance of a data and/or address bus interconnecting two chips or interconnecting two sub-components of a single chip; (c) a low frequency circuit design which minimizes power dissipation while providing a logic signal to various components or circuits of an implantable medical device; and (d) a resident design circuit which utilizes a resistor, inductor, capacitor configuration to minimize power dissipation to a component or circuit of an implantable medical device.